1. Field of the Invention
The invention pertains to a line-on glass type liquid crystal display panel that has been adapted to prevent signal interference between line-on glass signal lines.
2. Description of the Related Art
A liquid crystal display uses an electric field to control the light transmittance of a liquid crystalline material to display a picture. To this end, the liquid crystal display includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix. A driver circuit drives the liquid crystal display panel.
Gate lines and data lines are arranged in the liquid crystal display panel with the gate lines crossing the data lines. The liquid crystal cells are located at the areas where the gate lines cross the data lines. The liquid crystal display panel has a common electrode and pixel electrodes that are used to apply an electric field to each liquid crystal cell. Each pixel electrode is connected to any one of the data lines through the source and drain terminals of thin film transistors used as switching devices. The thin film transistors can be field effect transistors. The gate terminal of the thin film transistor is connected to any one of the gate lines to allow pixel voltage signals to be applied to the pixel electrode by-lines.
The driver circuit includes a gate driver for driving gate lines, a data driver for driving data lines, a timing controller controlling the gate driver and the data driver, and a power supply applying various drive voltages used in the liquid crystal display. The timing controller controls the drive timing of the gate driver and the data driver, and applies pixel data signals to the data driver. The power supply generates drive voltages such as a common voltage Vcom, a gate high voltage Vgh and a gate low voltage Vgl needed to input power to the liquid crystal display. The gate driver sequentially applies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel by-lines. The data driver applies the pixel voltage signal to each data line whenever the scan signal is applied to any one of the gate lines. Accordingly, the liquid crystal display controls the light transmittance by the electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal, thereby displaying a picture.
The data driver and the gate driver are directly connected to the liquid crystal display panel and are integrated into multiple of integrated circuits (IC). The integrated data drive IC and gate drive IC are each mounted on a tape carrier package (TCP) to connect to the liquid crystal display by a tape automated bonding (TAB) method or to mount on the liquid crystal display panel by a chip on glass (COG) method.
The drive IC's connected to the liquid crystal display panel by the TAB method through the TCP receive control signals and DC voltages inputted from the outside through the control lines of a printed circuit board (PCB) connected to the TCP, which are also connected reciprocally. More particularly, the data drive IC's are connected in series through the signal lines mounted on the data PCB and commonly receive the control signal and pixel data signal from the timing controller and the drive voltages from the power supply. The gate drive IC's are connected in series through the signal lines mounted on the gate PCB and commonly receive the control signals from the timing controller and the drive voltages from the power supply.
The drive IC's mounted on the liquid crystal display panel by a COG method are connected reciprocally by a line-on glass (LOG) method where the signal lines are mounted on the liquid crystal display panel, i.e., a lower glass, and receive the control signals and the drive voltages from the timing controller and the power supply.
Recently, liquid crystal displays have been thinned by removing the PCB in the LOG method, even when the drive IC's are connected to the liquid crystal display panel by the TAB method. Specifically, the signal lines connected to the gate drive IC, which need relatively fewer signal lines, are formed on the liquid crystal display panel by the LOG method, thereby removing the gate PCB. That is, the gate drive IC's of the TAB method are connected in series through the signal lines mounted on the lower glass of the liquid crystal display panel and commonly receive the control signals and the drive voltage signals (hereinafter, gate drive signals).
FIG. 1 shows an exemplary liquid crystal display where the gate PCB is removed in use of LOG type signal lines. The liquid crystal display includes a liquid crystal display panel 1, a multiple data TCP's 8 connected between the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCP's 14 connected to the other side of the liquid crystal display panel 1, data driver IC's 10 mounted on the data TCP's respectively, and gate driver IC's 16 mounted on the gate TCP's respectively.
The liquid crystal display panel 1 includes a lower substrate 2 provided with a thin film transistor array together with various signal lines, an upper substrate 4 provided with a color filter array, and liquid crystal injected between the lower substrate 2 and the upper substrate 4. In such a liquid crystal display panel 1, there is provided a picture display area 21 that contains liquid crystal cells provided at each intersection of gate lines 20 and data lines 18, and a picture is displayed in the picture display area 21. Data pads extended from the data line 18 and the gate pads extended from the gate line 20 are located in the outer part of the picture display area 21. Further, an LOG type signal line group 26 for transmitting the gate drive signal applied to the gate drive IC 16 is located at the outer area of the lower substrate 2.
The data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads electrically connected to the data drive IC 10 are formed on the data TCP 8. The input pads of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. Specifically, in the first data TCP 8, there is additionally formed a gate drive signal transmission group 22 electrically connected to the LOG type signal line group 26 on the lower substrate 2. The gate drive signal transmission group 22 applies the gate drive signals supplied from the timing controller and the power supply to the LOG type signal line group 26 through the data PCB 12.
The data drive IC's 10 convert the digital pixel data signal into analog pixel voltage signal, and applies the pixel voltage signal to the data lines 18 on the liquid crystal display panel.
The gate dive IC 16 is mounted on the gate TCP 14. The gate control signals and power signals applied to the gate TCP 14 are inputted into the gate dive IC 16 through the input terminal of the gate drive IC 16. And, the gate control signals and the power signals are outputted through the output terminal 30 of the gate drive IC 16 and applied to the gate drive IC 16 mounted on the next gate TCP 14 through the gate TCP 14 and the LOG signal line group 26.
The gate drive IC's 16 sequentially apply scan signals, i.e., gate high voltage signal VGH, in response to the input control signals. Further, the gate drive IC's 16 apply the gate low voltage signal VGL to the gate lines in a remaining period except for the period when the gate high voltage signal VGH is applied.
The LOG type signal line group 26 consists of signal lines each applying DC voltage signals applied from the power supply, i.e., a gate high voltage signal VGH, a gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND and a power voltage signal, and gate control signals applied from the timing controller, i.e., a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE. Further, the LOG type signal line group 26 includes a LOG type data pad group 32 connected to the data TCP 8 together with the data pads to which the data signal is applied, and a LOG type gate pad group 34 connected to the gate TCP 14 together with the gate pads to which the gate signal is applied.
The LOG type signal lines 26 of the LOG type liquid crystal display panel are formed of gate metal on the lower substrate 2, as shown in FIG. 3. In other words, the LOG type signal lines 26 are simultaneously formed of the same metal as the gate lines 20. For example, the LOG type signal lines 26 uses the gate metal such as AlNd.
The LOG type signal lines 26 of the related art liquid crystal display are formed adjacent to each other in a limited edge area on the lower substrate 2. Accordingly, the LOG type signal lines 26 have high impedance because the LOG type signal lines 26 include a relatively high line resistance and parasitic capacitance. This results in signal interference and electromagnetic interference (EMI) between the LOG type signal lines 26. Because of this, the gate signals applied to the gate drive IC 16 through the LOG type signal lines 26 are distorted.